1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a redundant memory cell circuit.
2. Description of the Prior Art
Generally, highly integrated semiconductor memory devices on the order of 64 megabits or above include redundant memory cells and circuits in addition to normal memory cells and circuits. Redundancy circuits are used when a fault occurs in a normal memory cell or circuit during fabrication of the memory device. A redundant memory cell circuit typically includes a programmable fuse formed of impurity-doped polysilicon which is cut when the redundant memory cell circuit is used as a substitute for a normal memory circuit having a fault. The fuse is typically cut using a laser beam and is thus often called a laser fuse. The laser fuse can be formed simultaneously with a bit line during fabrication of the semiconductor memory device. Therefore, laser fuses can be easily incorporated as components of redundant memory cell circuits.
A redundant memory circuit generally includes redundant memory cells, redundant memory cell lines, redundant fuse boxes, and auxiliary redundant decoders. The redundant memory cells are used as substitutes for defective memory cells and the redundant memory cell lines are used to drive the redundant memory cells. The redundant fuse boxes recognize the addresses of defective memory cells upon input of the addresses via input terminals and enable the redundant memory cell lines. The auxiliary redundant decoders decode the addresses of a plurality of defective memory cells for a plurality of redundant memory cell lines.
The redundant memory cell lines are enabled in a manner similar to the way that normal memory cell lines are enabled.
The redundant memory cell lines include both redundant word and bit lines. The redundant fuse boxes which enable the redundant memory cell lines include both row and column redundant fuse boxes that enable the redundant word and bit lines, respectively. Each row and column redundant fuse box has at least one row and column redundant fuse circuit. Similarly, the auxiliary redundant decoders include both auxiliary row and column decoders which decode row and column addresses that correspond to defective memory cells in the normal memory cell array and enable redundant word and bit lines, respectively.
FIG. 1 is a circuit diagram of a conventional row redundant fuse circuit in a row redundant fuse box. The conventional row redundant fuse circuit of FIG. 1 includes a precharge transistor 30, a state preserving circuit 40, a laser fuse array 50, a pass transistor array 60, and a redundant signal generating circuit 70.
The precharge transistor 30, which is a PMOS transistor gated by a precharge signal PRECH, has a source that is connected to a power supply terminal Vcc, and a drain connected to a first node 31. The precharge signal PRECH activates the precharge transistor 30 when a row address strobe signal RASB is in a precharge state, and deactivates the precharge transistor 30 when the row address strobe signal is in an active state.
The state preserving circuit 40 has input and output terminals each connected to the first node 31 to form a feed-back loop which feeds-back and recharges the state of the first node 31.
The laser fuse array 50 has a plurality of laser fuses each of which is connected in series with one of the transistors of pass transistor array 60 between the first node 31 and one of a series of ground terminals. The conventional row redundant fuse circuit recognizes the row address of a defective memory cell upon input of the row address to the row redundant fuse circuit. There are twice as many laser fuses in the laser fuse array 50 as there are bits of address information input to the row redundant fuse circuit. The address information is the row address information bits Rai to Ran and complementary row address information bits RaiB to RanB input to pass transistor array 60. Consequently, the number of laser fuses is the sum of the number of the row address information bits Rai to Ran and the number of complementary row address information bits RaiB to RanB.
The pass transistor array 60 receives the row address information bits Rai to Ran and the complementary row address information bits RaiB to RanB through the gates of the pass transistors. Therefore, the number of pass transistors also equals the sum of the number of the row address information bits Rai to Ran and the number of complementary address information bits RaiB to RanB.
The redundant signal generating circuit 70 receives the state of the first node 31 along with a predecode signal PREDE and generates a redundant signal REDi which transitions to an active high logic level H only if the first node state and the signal PREDE are simultaneously at high levels H. The signal PREDE becomes active after the row address strobe signal is activated.
The operation of a redundant memory cell as a substitute for a defective memory cell will now be described with reference to FIG. 1.
A row redundant fuse circuit corresponding to a redundant memory cell is encoded to recognize the row address of a defective normal memory cell which is to be replaced by the redundant memory cell. A subset of the laser fuses in laser fuse array 50, which are connected to pass transistors in pass transistor array 60 for receiving a combination of the row address bits Rai to Ran and complementary row address bits RaiB to RanB, which correspond to the address of the defective memory cell are shorted in the corresponding row redundant fuse circuit.
The operation of the conventional semiconductor memory device will be further described with reference to FIGS. 1, 2, and 3. FIG. 2 is a timing diagram showing the waveforms for several signals when an address corresponding to a defective memory cell is input to the row redundant fuse circuit of FIG. 1. Here, Rai, .phi..sub.nl, .phi..sub.nw, and .phi..sub.rw indicate a row address input signal, the first node signal, a normal word line enable signal, and a redundant word line enable signal, respectively. Also, AP indicates the address information of the defective memory cell.
As illustrated by the timing diagrams of the precharge signal PRECH and the first node signal .phi..sub.nl, when the row address strobe signal RASB is at a high-level, and thus is in a precharge state, the precharge transistor 30 switches on and precharges the first node 31 to a high logic state H. Subsequently, when the row address strobe signal RASB transitions to an active low state, the precharge transistor 30 switches off. At this point, the row address information for a defective memory cell is input on row address bits Rai to Ran and complementary row address bits RaiB to RanB to the gates of the pass transistors of the pass transistor array 60, as illustrated in the timing diagrams of the address input signal Rai of FIG. 2.
When the row address corresponding to the defective memory cell is input to the pass transistors, then, due to the pattern of cut fuses in laser fuse array 50, the path through which first node 31 can be discharged is blocked by the fuses of laser fuse array 50 combined with the pass transistors of transistor array 60. Therefore, as shown in the timing diagrams of the first node state .phi..sub.nl, and the redundant signal REDi of FIG. 2, the state of the first node 31 signal .phi..sub.nl remains at a high logic state H when the signal PREDE is enabled. Thus, the redundant signal REDi output from the redundant signal generating circuit 70 is activated. As shown in the timing diagrams of the redundant signal REDi and the redundant word line enable signal .phi..sub.rw, when the redundant signal REDi is activated, the redundant word line enable signal .phi..sub.rw becomes high and enables a redundant word line corresponding to the redundant memory cell.
FIG. 3 is a timing diagram illustrating the function of the redundant fuse circuit of FIG. 1 when the address information for a normal memory cell is input on row address bits Rai to Ran and complementary row address bits RaiB to RanB. The signal AN indicates the address information for the normal memory cell.
When the row address information for the normal memory cell is input to the gates of the pass transistors of pass transistor array 60 during an active cycle of the row address strobe signal RASB, then a path will form through the laser fuse array 50 and the pass transistor array 60 through which the charge formed on the first node 31 when RASB is inactive can be discharged to a ground terminal. The only way that no path will be formed from the first node 31 to ground is when the row address information corresponding to the defective memory cell for which the laser fuses are shorted is input on row address bits Rai to Ran and complementary row address bits RaiB to RanB. As shown in the timing diagrams of the first node signal .phi..sub.nl and the redundant signal REDi of FIG. 3, the first node signal .phi..sub.nl shifts from a high-level H to a low-level L. Thus, though the signal PREDE is enabled to a high-level H during the active cycle of the row address strobe signal RASB, the redundant signal REDi is held low by the redundant signal generating circuit 70. Therefore, a normal word line enable signal corresponding to the row address is enabled and drives a normal word line.
Redundant bits lines corresponding to the column addresses for defective memory cells are enabled in a manner similar to the method for enabling word lines corresponding to the row addresses of defective memory cells described above.
The product yield for highly integrated memory devices can be significantly increased by providing redundant memory circuits that can replace defective memory cells.
However, in conventional semiconductor memory device which utilize the conventional redundant memory cell circuit described above, the redundant fuse circuit experiences an undesirable instantaneous peak current that is generated when the address of a normal memory cell is input to the pass transistors of a pass transistor array 60. This problem will be described with reference to FIGS. 1 and 3, using the row redundant fuse circuit of FIG. 1 as an example.
As shown in FIG. 3, the first node 31 logic state .phi..sub.nl is precharged to a high level and remains active while the row address of a memory cell is input to the gates of the pass transistors of transistor array 60. The laser fuses connected to the pass transistors have already been shorted to correspond to a combination of row address bits Rai to Ran and complementary row address bits RaiB to RanB for a defective memory cell. Therefore, if the row address strobe signal RASB transitions to an active low level and the row address for a normal memory cell is input, then an instantaneous peak current will flow since the charge on the first node 31 is discharged through paths formed by the pass transistors connected to non-shorted laser fuses. Consequently, an instantaneous peak current will be generated during every active cycle of the row address strobe signal RASB except when a specific row address for a defective memory cell is input.
In addition, since redundant fuses not used for the defective memory cell are not cut, the peak current is generated during every active cycle of the address strobe signal RASB regardless of the input address information.
A highly integrated semiconductor device requires a multitude of redundant fuse boxes (e.g., about 100 redundant fuse boxes for a 64 megabits semiconductor device), and each redundant fuse box includes at least one redundant fuse circuit. Furthermore, the number of pass transistors of the transistor array 60 in the redundant fuse circuit is also related to the number of address bits used in a semiconductor memory device and the number of address bits increases with increasing memory capacity. Therefore, the peak current generated during each active cycle of the row address strobe signal RASB becomes a serious problem which affects the reliability of highly integrated semiconductor memory devices.